Digital Logic MCQ BCA First Semester 2023 Batch

Digital Logic MCQ BCA First Semester 2023 Batch

Tribhuvan University
Faculty of Humanities & Social Sciences

Full Marks: 60 Pass Marks: 24
Batch: 2023
Semester: I

i. When output will go high in AND Gate?

a) If all inputs are high b) If any input is high

c) If all inputs are low d) If any input is low states.

ii. A decimal counter has _______ states.

a)5 b)10

c)15 d)20

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iii. Which gates in Digital Circuits are required to convert a NOR-based SR latch to an SR flip-flop?

a) Two 2 input AND gates b) Two 3 input AND gates

c) Two 2 input OR gates d) Two 3 input OR gates

iv. What must be used along with synchronous control inputs to trigger a change in the flip flop?

a) 0 b) 1

c) Clock d) Previous output

V. What will be the output from a D flip-flop if the clock is low and D = 0?

a) 0 b) 1

c) No change d) Toggle between 0 and 1

vi. What value is to be considered for a “don’t care condition”?

a) 0 b) 1

c) Either 0 or 1 d) Any number except 0 and 1

vii. Which of the following gives the correct number of multiplexers required to build a 32 x 1 multiplexer?

a) Two 16 x 1 mux b) Three 8 x 1mux

c) Two 8 x 1 mux d) Three 16 x 1 mux

viii. The result “X + XY =X” follows which of these laws?

a) Consensus law b) Distributive law

c) Duality law d) Absorption law

ix. The full form of PLD is_______

a) Programmable Load Devices b) Programmable Logic Data

c) Programmable Logic Devices d) Programmable Loaded Devices

X. How many possible outputs would a decoder have with a 6-bit binary input?

a) 16 b) 64

c) 32 d) 128

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Abiral Acharya

Myself (Abiral Acharya) an undergraduate BCA student from Mechi Multiple Campus, Jhapa.

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